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PACDN006 6 Channel ESD Protection Array
Features
* * * * * * * Six channels of ESD protection +8 kV contact, +15 kV air ESD protection per per channel (IEC 61000-4-2 standard) +15 kV of ESD protection per channel (HBM) Low loading capacitance (3pF typical) Low leakage current is ideal for battery-powered devices Available in miniature 8-pin MSOP or SOIC packages Lead-free versions available
Product Description
The PACDN006 is a diode array designed to provide 6 channels of ESD protection for electronic components or sub-systems. Each channel consists of a pair of diodes which steers an ESD current pulse to either the positive (VP) or negative (VN) supply. The PACDN006 protects against ESD pulses up to 15kV Human Body Model (100 pF capacitor discharging through a 1.5K resistor), and 8kV contact discharge, per International Standard IEC 61000-4-2. This device is particularly well-suited for portable electronics (e.g., cellular phones, PDAs, notebook computers) because of its small package footprint, high ESD protection level, and low loading capacitance. It is also suitable for protecting video output lines and I/O ports in computers and peripherals and is ideal for a wide range of consumer electronics products. The PACDN006 is available with optional lead-free finishing, supporting the current global industry movement to lead free manufacturing.
Applications
* * * * * * * Consumer electronic products Cellular phones PDAs Notebook computers Desktop PCs Digital cameras and camcorders VGA (video) port protection for desktop and portable PCs
Typical Application Circuit
VCC
Electrical Schematic
8
3
7
VP
6
5
PACDN006
1 24568
7
0.22uF*
I/O Port Buffers
Expansion Connector
VN
Handheld/PDA ESD Protection
* Decoupling capacitor must be placed as close as possible to Pin7.
1
2
3
4
(c) 2004 California Micro Devices Corp. All rights reserved. 03/16/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
1
PACDN006
PACKAGE / PINOUT DIAGRAMS
TOP VIEW
CH 1 CH 2 VN CH 3 1 2 3 4 8 7 6 5 CH 6 VP CH 5 CH 4 CH 1 CH 2 VN CH 3
TOP VIEW
1 2 3 4 8 7 6 5 CH 6 VP CH 5 CH 4
8-pin MSOP
Note: MSOP and SOIC packages are different in size, pitch, and proportion. These drawings are not to scale.
8-pin SOIC
PIN DESCRIPTIONS
PIN 1 2 3 4 5 6 7 8 NAME CH 1 CH 2 VN CH 3 CH 4 CH 5 VP CH 6 TYPE I/O I/O GND I/O I/O I/O Supply I/O DESCRIPTION ESD Channel. ESD Channel. Negative voltage supply rail or ground reference rail. ESD Channel. ESD Channel. ESD Channel. Positive voltage supply rail. ESD Channel.
Ordering Information
PART NUMBERING INFORMATION
Standard Finish Pins 8 8 Package SOIC MSOP Ordering Part Number1 PACDN006S PACDN006M Part Marking PACDN006S D006 Lead-free Finish Ordering Part Number1 PACDN006SM PACDN006MR Part Marking PACDN006SM 006R
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
(c) 2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
03/16/04
PACDN006
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (VP - VN) Diode Forward DC Current (Note 1) Operating Temperature Range Storage Temperature Range DC Voltage at any channel input Package Power Rating SOIC Package MSOP Package
Note 1: Only one diode conducting at a time.
RATING 6.0 20 -40 to +85 -65 to +150 (VN - 0.5) to (VP + 0.5) 350 200
UNITS V mA C C V mW mW
STANDARD OPERATING CONDITIONS
PARAMETER Operating Temperature Range Operating Supply Voltage (VP - VN) RATING -40 to +85 0 to 5.5 UNITS C V
ELECTRICAL OPERATING CHARACTERISTICS(SEE NOTE 1)
SYMBOL IP VF VESD PARAMETER Supply Current Diode Forward Voltage ESD Protection Peak Discharge Voltage at any channel input, in system a) Human Body Model, MIL-STD-883, Method 3015 b) Contact Discharge per IEC 61000-4-2 c) Air Discharge per IEC 61000-4-2 Channel Clamp Voltage Positive Transients Negative Transients Channel Leakage Current Channel Input Capacitance @ 1 MHz, VP=5V, VN=0V, VIN=2.5V; Note 2 applies CONDITIONS (VP-VN)=5.5V IF = 20mA Note 3 Notes 2,4 Note 5 Note 5 @15kV ESD HBM VP + 13.0 VN - 13.0 +0.1 3 +1.0 5 V V A pF 15 + 8 + + 15 kV kV kV 0.65 MIN TYP MAX 10 0.95 UNITS A V
VCL
ILEAK CIN
Note 1: All parameters specified at TA=25C unless otherwise noted. VP = 5V, VN = 0V unless noted. Note 2: These parameters guaranteed by design and characterization. Note 3: From I/O pins to VP or VN only. VP bypassed to VN with a 0.22F ceramic capacitor (see Application Information for more details). Note 4: Human Body Model per MIL-STD-883, Method 3015, CDischarge = 100pF, RDischarge = 1.5K, VP = 5.0V, VN grounded. , Note 5: Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330 VP = 5.0V, VN grounded.
(c) 2004 California Micro Devices Corp. All rights reserved. 03/16/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
3
PACDN006
Performance Information
Input Capacitance vs. Input Voltage
5 4
CIN (pF)
3 2 1 0 0 1 2 3 4 5
VIN
(VP = 5V, VN = 0V, 0.1 F chip capacitor between VP and VN)
Typical Variation of CIN vs. VIN
(c) 2004 California Micro Devices Corp. All rights reserved.
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
03/16/04
PACDN006
Application Information
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/ Ground rails as well as the signal trace segment between the signal input (typically a connector) and the ESD protection device. Refer to Figure 1, which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on the line being protected is:
VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt + L2 x d(IESD ) / dt
a ROUT of 1 ohm would result in a 10V increment in VCL for a peak IESD of 10A. If the inductances and resistance described above are close to zero, the rail-clamp ESD protection diodes will do a good job of protection. However, since this is not possible in practical situations, a bypass capacitor must be used to absorb the very high frequency ESD energy. So for any brand of rail-clamp ESD protection diodes, a bypass capacitor should be connected between the VP pin of the diodes and the ground plane (VN pin of the diodes) as shown in the Application Circuit diagram below. A value of 0.22F is adequate for IEC-61000-4-2 level 4 contact discharge protection (+8kV). Ceramic chip capacitors mounted with short printed circuit board traces are good choices for this application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. For extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply voltage. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance.
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here d(IESD)/dt can be approximated by IESD/t, or 30/(1x10-9). So just 10nH of series inductance (L1 and L2 combined) will lead to a 300V increment in VCL! Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased negative voltage on the line being protected. Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit a much higher output impedance to fast transient current spikes. In the VCL equation above, the VSUPPLY term, in reality, is given by (VDC + IESD x ROUT), where VDC and ROUT are the nominal supply DC output voltage and effective output impedance of the power supply respectively. As an example,
VP
Additional Information
See also California Micro Devices Application Notes AP209, "Design Considerations for ESD Protection" and AP219, "ESD Protection for USB 2.0 Systems""
L2
POSITIVE SUPPLY RAIL
PATH OF ESD CURRENT PULSE IESD
D1 0.22F
ONE CHANNEL OF PACDN006
L1
CHANNEL INPUT
20A
LINE BEING PROTECTED
D2
SYSTEM OR CIRCUITRY BEING PROTECTED
VCL
GROUND RAIL
0A
VN
CHASSIS GROUND
Figure 1. Application of Positive ESD Pulse between Input Channel and Ground
(c) 2004 California Micro Devices Corp. All rights reserved. 03/16/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
5
PACDN006
Mechanical Details
MSOP Mechanical Specifications PACDN006 devices are packaged in 8-pin MSOP and SOIC packages. Dimensions for these packages are presented on the following pages. For complete information on the MSOP-8 or SOIC-8 packages, see the specific California Micro Devices Package Information document. Mechanical Package Diagrams
TOP VIEW
D
8 7 6 5
PACKAGE DIMENSIONS
Package Pins Dimensions A A1 B C D E e H L # per tube # per tape and reel 2.90 2.90 4.78 0.52 Millimeters Min 0.87 0.05 0.18 3.10 3.10 4.98 0.54 0.114 0.114 0.188 0.017 Max 1.17 0.25 Min 0.034 0.002 MSOP 8 Inches Max 0.046 0.010
H
Pin 1 Marking
E
1
2
3
4
SIDE VIEW
0.30 (typ)
0.012 (typ) 0.007 0.122 0.122
SEATING PLANE
A A1 B e
END VIEW
0.65 BSC
0.025 BSC 0.196 0.025
C
80 pieces* 4000 pieces
L
Controlling dimension: inches
* This is an approximate number which may vary.
Package Dimensions for MSOP-8
(c) 2004 California Micro Devices Corp. All rights reserved.
6
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
03/16/04
PACDN006
Mechanical Details (cont'd)
SOIC Mechanical Specifications Mechanical Package Diagrams
TOP VIEW
PACKAGE DIMENSIONS
Package Pins Dimensions A A1 B C D E e H L # per tube # per tape and reel Millimeters Min 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.40 Max 1.75 0.25 0.51 0.25 5.00 4.19 6.20 1.27 Min 0.053 0.004 0.013 0.007 0.189 0.150 0.228 0.016 SOIC 8 Inches Max 0.069 0.010 0.020 0.010 0.197 0.165
D
8 7 6 5
H
Pin 1 Marking
E
1.27 BSC
0.050 BSC 0.244 0.050
1
2
3
4
SIDE VIEW
100 pcs* 2500 pcs Controlling dimension: inches
SEATING PLANE
A A1 B e
END VIEW
* This is an approximate number which may vary.
C
L Package Dimensions for SOIC-8
(c) 2004 California Micro Devices Corp. All rights reserved. 03/16/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
7

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